Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
Voltage level translators or transceivers may be used for having integrated circuits of different logic high voltage levels communicate with one another. These voltage level transceivers or translators provide voltage level shifting, and thus may more generally be thought of as “level shifters.”
There are various known applications where level shifters may be employed. Conventionally, level shifters implemented with “push-pull” input/output drivers are used for communicating between two integrated circuits, for example such as where a host device communicates with a peripheral device.
More recently, “open-drain” circuitry is being used instead of push-pull circuitry for input/output circuitry. Examples of open-drain configurations include Secure Digital (“SD”), MMC, I2C, SPI, and Microwire, among other known open-drain configurations. More particularly, in the SD segment, a host device, such as a microprocessor, may communicate with an SD or SDIO peripheral device. By peripheral device, it is meant an integrated circuit external to the host integrated circuit. Because host and peripheral integrated circuits may have different logic high voltage levels, voltage level translation and/or logic isolation between such host and peripheral device may be needed. Additionally, a host device, such as a microprocessor, may only have one controller for communicating with one peripheral device at a time.
Accordingly, it would be both desirable and useful to provide level shifting means for open-drain uses. Moreover, it would be additionally both desirable and useful to provide level shifting means for open-drain uses that allows a single controller to multiplex with more than one peripheral device. Furthermore, it would be both desirable and useful to provide a bidirectional multiplexing means that allows a single controller to communicate with more than one open-drain peripheral device with or without level shifting for logical isolation.